1. Field of the Invention
The present invention is related to a class “AB” amplifier circuit and a display apparatus including a display panel which is driven by a class AB amplifier circuit.
2. Description of Related Art
As one of the application fields of a class AB amplifier circuit, there is known TFT_LCD (Thin Film Transistor_Liquid Crystal Display) driver LSI (hereinafter, to be referred to as a liquid crystal driver). The class AB amplifier circuit for a liquid crystal driver drives capacitive loads (pixel capacitances) provided for a liquid crystal panel. Such a class AB amplifier circuit is required to have a low consumption current amount and to be able to charge and discharge the capacitive load at high speed.
In recent years, a large-sized TFT_LCD panel of 42 inches or more for a TV needs to be drive by the class AB amplifier circuit arises. The large-sized TFT_LCD panel is large in load capacitance and high in a drive frequency. Also, because a current consumption amount increases as the drive speed increases, heat generation in a chip sometimes becomes a problem. From the above reasons, the class AB amplifier circuit for the liquid crystal driver needs to be possible to increase the drive speed and to have a low current consumption amount.
Moreover, in recent years, as the price of the TFT_LCD panel falls, the cost reduction of the liquid crystal driver is required. As an effective measure of the reduction in cost of the liquid crystal driver, it could be considered to shrink the chip size of the driver. A plurality of class AB amplifier circuits (e.g. 400 to 700 circuits) connected in a voltage follower configuration are provided for a buffer circuit in the liquid crystal driver. That is, an occupation rate of the class AB amplifier circuits in the liquid crystal driver is high. Therefore, the shrinkage in the chip size of the class AB amplifier circuit is a key of the chip shrinkage of the liquid crystal driver.
In Japanese Patent Application Publication (JP 2005-124120A: first conventional example), a class AB amplifier circuit is described which is used for the liquid crystal driver and which has a low current consumption amount. FIG. 1 is a circuit diagram showing a configuration of the class AB amplifier circuit described in the first conventional example. This class AB amplifier circuit is so-called Rail-to-Rail amplifier.
Referring to FIG. 1, the class AB amplifier circuit includes an input stage circuit 10 which receives signals INP and INM, which are complementary signals, a middle stage circuit 20 which is connected with the input stage circuit 10 through nodes N1 and N2, and a last stage circuit 30 which is connected with the middle stage circuit 20 through nodes N3 and N4 and outputs an output signal OUT.
The input stage circuit 10 includes a differential circuit 101 which outputs an output to the node N1 in accordance to the input signals INP and INM, and a differential circuit 102 which outputs an output to the node N2 in accordance with the input signals INP and INM. The differential circuit 101 includes an N-channel MOS transistor MN11 and an N-channel MOS transistor MN12, which form a differential pair. The differential circuit 102 includes a P-channel MOS transistor MP11 and a P-channel MOS transistor MP12, which form a differential pair. By such configuration, the differential circuit 102 operates in an input voltage range in which the differential circuit 101 does not operate, and the differential circuit 101 operates in an input voltage range in which the differential circuit 102 does not operate. Thus, a differential stage operating in the whole input voltage range can be obtained. That is, the class AB amplifier circuit in the first conventional example realizes the Rail-to-Rail configuration.
Hereinafter, the configuration and operation of the class AB amplifier circuit will be described below. At first, the configuration of the differential circuit 101 will be described. The N-channel MOS transistor MN11 and the N-channel MOS transistor MN12 form a first differential pair to have their sources connected in common. The N-channel MOS transistor MN15 is connected between the first differential pair and a negative power supply (the power supply of a low voltage side) VSS. In detailed, a source of the N-channel MOS transistor MN15 is connected with the negative power supply VSS, a drain thereof is connected with the sources of the N-channel MOS transistor MN11 and the N-channel MOS transistor MN12 in common and a gate thereof is connected with a constant voltage source terminal BN11. A bias voltage (the constant voltage) is supplied to the constant voltage source terminal BN11 and the N-channel MOS transistor MN15 functions as a constant current source. The differential circuit 101 further includes P-channel MOS transistors MP13 and MP14. Sources of the P-channel MOS transistor MP13 and the P-channel MOS transistor MP14 are connected with a positive power supply (the power supply of a high voltage side) VDD in common. A drain and gate of the P-channel MOS transistor MP13, and a gate of the P-channel MOS transistor MP14 are connected with the drain of the N-channel MOS transistor MN11 in common. A drain of the P-channel MOS transistor MP14 and the drain of the N-channel MOS transistor MN12 are connected with node N1 in common.
Next, the configuration of the differential circuit 102 will be described. The P-channel MOS transistor MP11 and the P-channel MOS transistor MP12 form a second differential pair to have their sources connected in common. The P-channel MOS transistor MP15 is connected between a second differential pair and the positive power supply VDD. In detailed, the source of the P-channel MOS transistor MP15 is connected with the positive power supply VDD. A drain thereof is connected with the sources of the P-channel MOS transistor MP11 and the P-channel MOS transistor MP12 in common. A gate thereof is connected with a constant voltage source terminal BP11. A bias voltage (a constant voltage) is supplied to the constant voltage terminal BP11 and the P-channel MOS transistor MP15 functions as the constant current source. The differential circuit 102 further includes the N-channel MOS transistors MN13 and MN14. The differential circuit 102 further includes the P-channel MOS transistors MP11 and MP12 and. Sources of the N-channel MOS transistor MN13 and the N-channel MOS transistor MN14 are connected with the negative power supply VSS in common. A drain and gate of the N-channel MOS transistor MN13 and a gate of the N-channel MOS transistor MN14 are connected to have a drain of the P-channel MOS transistor MP11 in common. A drain of the N-channel MOS transistor MN14 and a drain of the P-channel MOS transistor MP12 are connected with the node N2 in common. A gate of the P-channel MOS transistor MP11 and a gate of the N-channel MOS transistor MN11 are connected with the input terminal INM in common. A gate of the P-channel MOS transistor MP12 and a gate of the N-channel MOS transistor MN12 are connected with the input terminal INP in common.
The middle stage circuit 20 includes an N-channel MOS transistor MN22 and a P-channel MOS transistor MP22 which function as a floating current source 201, a P-channel MOS transistor MP21 connected with the positive power supply VDD and functioning as a constant current source, and an N-channel MOS transistor MN21 connected with the negative power supply VSS and functioning as a constant current source. A gate of the P-channel MOS transistor MP22 is connected with a constant voltage source terminal BP22 to which a bias voltage is supplied. A source of the P-channel MOS transistor MP22 is connected with a drain of the N-channel MOS transistor MN22, a drain of the P-channel MOS transistor MP21, and nodes N1 and N3 in common. A drain of the P-channel MOS transistor MP22 is connected with a source of the N-channel MOS transistor MN22, a drain of the N-channel MOS transistor MN21, and nodes N2 and N4 in common. A gate of the N-channel MOS transistor MN22 is connected with a constant voltage source terminal BN22 to which a bias voltage is supplied. A source of the N-channel MOS transistor MN22 is connected with the drain of the P-channel MOS transistor MP22, the drain of the N-channel MOS transistor MN21, and the nodes N2 and N4 in common. The drain of the N-channel MOS transistor MN22 is connected with the source of the P-channel MOS transistor MP22, the drain of the P-channel MOS transistor MP21, and the nodes N1 and N3 in common.
The last stage circuit 30 is an AB class output stage in which an output OUT is controlled by the floating current source 201 in the middle stage circuit 20. The last stage circuit 30 includes a P-channel MOS transistor MP31 whose gate is connected with the floating current source 201 through the node N3, and an N-channel MOS transistor MN31 whose gate is connected with the floating current source 201 through the node N4. A source of the P-channel MOS transistor MP31 is connected with the positive power supply VDD and a source of the N-channel MOS transistor MN31 is connected with the negative power supply VSS. A drain of the P-channel MOS transistor MP31 and a drain of the N-channel MOS transistor MN31 are connected with an output terminal OUT in common. Also, the output terminal OUT is connected with the floating current source 201 through phase compensation capacitances C1 and C2. In detail, one end of the phase compensation capacitance C1 is connected with the floating current source 201 through the node N3 and the other end thereof is connected with the output terminal OUT. One end of the phase compensation capacitance C2 is connected with the floating current source 201 through the node N4 and the other end thereof is connected with the output terminal OUT.
An idling current in the class AB amplifier circuit in the first conventional example is determined by the floating current source 201. The power consumption amount of the idling current when the output terminal OUT is directly connected with the input terminal INM to use the class AB amplifier circuit as a voltage follower circuit will be described. The class AB amplifier circuit used as the voltage follower is an amplifier circuit having high input impedance and a low output impedance, and outputs a voltage supplied to the input terminal INP to the output terminal OUT just as it is.
Here, it is supposed that each of the drain currents of the P-channel MOS transistor MP15 and the N-channel MOS transistor MN15 as the constant current source is 2I in the input stage circuit 10. When the voltage of the input terminal INP and that of the output terminal OUT are same, a half I of the drain current flowing through each of the P-channel MOS transistor MP15 and the N-channel MOS transistor MN15 flows through the drains of the P-channel MOS transistor MP11, the P-channel MOS transistor MP12, the N-channel MOS transistor MN11, and the N-channel MOS transistor MN12.
When the voltage at the input terminal INP is shifted to the side of a higher voltage as compared with the voltage at the output terminal OUT, current of the same value as the drain current 2I which flows through the input stage constant current source (the P-channel MOS transistor MP15 or the N-channel MOS transistor MN15) flows through the P-channel MOS transistor MP11 and the N-channel MOS transistor MN12. However, any current does not flow through the P-channel MOS transistor MP12 and the N-channel MOS transistor MN11.
On the other hand, because the P-channel MOS transistor MP13 and the P-channel MOS transistor MP14 form a current mirror circuit, the current which flows through the P-channel MOS transistor MP14 becomes zero. Similarly, because the N-channel MOS transistor MN13 and the N-channel MOS transistor MN14 form a current mirror circuit, the current which flows through the N-channel MOS transistor MN14 becomes 2I.
The gate voltage of the P-channel MOS transistor MP31 in the last stage circuit 30 falls because of a difference “−2I” between the current value “2I” of the N-channel MOS transistor MN12 and the current value “0” of the P-channel MOS transistor MP14. Also, the gate voltage of the N-channel MOS transistor MN31 in the last stage circuit 30 falls because of a difference “−2I” between the current value “2I” of the N-channel MOS transistor MN14 and the current value “0” of the P-channel MOS transistor MP12. Thus, the voltage of the output terminal OUT follows the voltage of the input terminal INP and changes to the side of the higher voltage. At this time, the phase compensation capacitance C2 functions as a coupling capacitance, to increase the gate voltage of the N-channel MOS transistor MN31 with the change of the voltage at the output terminal OUT. When the gate voltage of the N-channel MOS transistor MN31 rises, a penetrating current flows through a route from the positive power supply VDD to the negative power supply VSS through the P-channel MOS transistor MP31 and the N-channel MOS transistor MN31.
When the voltage of the input terminal INP is changed to the side of the lower voltage as compared with the voltage of the output terminal OUT, a current does not flow through the P-channel MOS transistor MP11 and the N-channel MOS transistor MN12. However, a current of the same value as the drain current 2I flows through the P-channel MOS transistor MP12 and the N-channel MOS transistor MN11. On the other hand, because the P-channel MOS transistor MP13 and the P-channel MOS transistor MP14 form the current mirror circuit, the current which flows through the P-channel MOS transistor MP14 becomes 2I. Similarly, because the N-channel MOS transistor MN13 and the N-channel MOS transistor MN14 form the current mirror circuit, the current which flows through the N-channel MOS transistor MN14 becomes zero.
The gate voltage of the P-channel MOS transistor MP31 rises because of a difference “+2I” between the current value “0” of the N-channel MOS transistor MN12 and the current value “2I” of the P-channel MOS transistor MP14. Also, the gate voltage of the N-channel MOS transistor MN31 rises because of a difference “+2I” between the current value “0” of the N-channel MOS transistor MN14 and the current value “2I” of the P-channel MOS transistor MP12. Therefore, the voltage at the output terminal OUT follows the voltage of the input terminal INP and changes to the side of the lower voltage. At this time, the phase compensation capacitance C1 functions as a coupling capacitance, to decrease the gate voltage of the P-channel MOS transistor MP31 with the change of the voltage of the output terminal OUT. When the gate voltage of the P-channel MOS transistor MP31 falls, the penetrating current flows through the course from the positive power supply VDD to the negative power supply VSS through the P-channel MOS transistor MP31 and the N-channel MOS transistor MN31.
As described above, in the class AB amplifier circuit of the first conventional example, the voltage of the output terminal OUT follows the voltage of the input terminal INP.
Also, the class AB amplifier circuit using a folded cascade type differential amplifying circuit is described in Japanese Patent Application Publications (JP-P2006-094533A: second conventional example; JP-A-Heisei 06-326529: third conventional example).
In order to realize a Rail-to-Rail system, the class AB differential amplifying circuit in the second and third conventional examples includes an input stage circuit having two differential pairs to which a differential signal is supplied, a middle stage circuit having two cascode circuits respectively connected with outputs of the two differential pairs, and a last stage circuit connected with the middle stage circuit to output an output signal according to the differential signal.
The middle stage circuit includes a floating current source to which a bias voltage is supplied. The last stage circuit is a class AB output stage circuit in which an idling current is controlled with the floating current source. Also, in the class AB amplifier circuit in the second conventional example, a phase compensation capacitance is provided between the middle stage circuit and the last stage circuit. One end of the phase compensation capacitance is connected with a connection node of the differential pair and the cascode circuit and the other end thereof is connected with the output terminal OUT.
A power consumption amount when the AB class differential amplifying circuit in the first conventional example is used as a voltage follower circuit to drive a liquid crystal panel will be described. When the voltage of the input terminal INP of the class AB differential amplifying circuit is changed to the side of a higher voltage as compared with the voltage of the output terminal OUT, the voltage of the output terminal OUT follows the voltage of the input terminal INP and changes to the side of the higher voltage, as described above. At this time, the phase compensation capacitance C2 functions as the coupling capacitance and the penetrating current flows through the route from the positive power supply VDD to the negative power supply VSS through the P-channel MOS transistor MP31 and the N-channel MOS transistor MN31. Similarly, when the voltage at the input terminal INP is changed to the side of a lower voltage as compared with the voltage of the output terminal OUT, the phase compensation capacitance C1 functions as the coupling capacitance and the penetrating current flows through the route from the positive power supply VDD to the negative power supply VSS through the P-channel MOS transistor MP31 and the N-channel MOS transistor MN31. Such a penetrating current does not contribute to charging and discharging operations to a capacitive load in the liquid crystal panel at all.
Next, a case to use the class AB amplifier circuit in the second or third conventional example as voltage follower circuit will be described. The middle stage circuit in the class AB amplifier circuit adds a current outputted from a differential pair of an input stage circuit. Also, it is necessary for a current which is larger than a current from a constant current source connected with the input stage circuit to flow through a floating current source in the middle stage circuit. For example, supposing that the current of the constant current source in the input stage circuit is 2I, in the class AB amplifier circuit of the first conventional example, it is possible to design the amplifier circuit under the condition that the current is “4I” which flows through the input stage circuit, and the current value is “I” which flows through the middle stage circuit. On the other hand, in the class AB amplifier circuit the second conventional example, it is necessary that the current is “4I” which flows through the input stage circuit, and the current is “6I” which flows through the middle stage circuit. That is, the current consumption amount of the class AB amplifier circuit in the second conventional example is twice the current consumption amount of the class AB amplifier circuit in the second conventional example.
Also, the class AB amplifier circuit of a folded cascade type in the second conventional example uses many elements and does not suit for chip shrinkage. As described above, a plurality of class AB amplifier circuits (400-700 circuits) connected to form voltage follower circuits as buffer circuits are included in the liquid crystal driver. Therefore, it is strongly required to decrease the power consumption amount and the chip area of the class AB amplifier circuit.